Peeter Joot's (OLD) Blog.

Math, physics, perl, and programming obscurity.

The point of an isync (or similar memory barrier)

Posted by peeterjoot on July 29, 2010

The following simple code fragment was used today when asked about the effect of an isync

v = atomic.fetchAndAdd( 0 ) ;

__isync() ;

if ( v == w )
{
   foo( pSharedMem->blah ) ;
} 

The isync will prevent loads and stores that occur after the atomic no-op operation from occuring ahead of time. For example, with the isync omitted, it could be as if the following code was executed instead:

blahValue = pSharedMem->blah ;

v = atomic.fetchAndAdd( 0 ) ;

if ( v == w )
{
   foo( blahValue ) ;
} 

If you want the pSharedMem->blah to happen strictly after the atomic read, then you’ll need an isync in between.

The excellent question was posed: “if pSharedMem->blah was declared volatile is the compiler allowed to still do this reordering?”

It is important to note that the code reordering of interest here may not actually have anything do with the compiler.

The compiler can generate the code in program order, but that doesn’t have to be the order that the hardware “executes it”.

That also doesn’t mean that you don’t may not also have to do something special to get the code to be generated in program order. For most platforms the compiler atomic intrinics are also implicit instruction scheduling fences, or have variations that include such fences to prevent reordering. The HP compiler is one where instruction scheduling fences for atomic instructions are not the default, so one has to add these explicitly in the implementation of an atomic library API.

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